Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
There is a trend toward large-scale chip multiprocessors that include a relatively large number of processor cores, with core counts as high as hundreds or thousands envisioned in the near future. Such processors can greatly reduce processing time for applications that have high levels of concurrency, such as applications in which multiple computations can be executed simultaneously or in parallel with each other. However, as this trend continues, efficient use of all processor cores in high core-count chip multiprocessors may become more difficult, since threshold voltage can no longer be scaled down without exponentially increasing the static power consumption incurred due to leakage current in the chip multiprocessor. As a result, a power budget available per core in high core-count chip multiprocessors is projected to decrease in each future technology generation. This situation results in a phenomenon referred to as the “power wall,” “utility wall,” or “dark silicon,” where an increasing fraction of a high core-count chip multiprocessor may not be powered at full frequency or powered on at all. Thus, performance improvements in such chip multiprocessors may be strongly contingent on energy efficiency, e.g., performance/watt or operations/joule.